Silicon Proven Hardware Acceleration of Post-Quantum Cryptography on RISC-V

Hardware/Software co-designs offer a promising way to support different Post-quantum cryptographic algorithms on one platform. Especially, as these algorithms are not yet standardized, the flexibility of such an approach is important to support possible future algorithm changes in the standardization process. To explore the design space of such RISC-V based HW/SW co-designs, we present three different ASICs, designed since 2020, accelerating different subsets of the PQ-algorithms in the NIST competition, one in UMC 65nm and two in Globalfoundries‘ 22nm. All designs offer significant performance advantages over pure software implementations on the same platform, while largely maintaining the flexibility of a pure software approach.      «

Hardware/Software co-designs offer a promising way to support different Post-quantum cryptographic algorithms on one platform. Especially, as these algorithms are not yet standardized, the flexibility of such an approach is important to support possible future algorithm changes in the standardization process. To explore the design space of such RISC-V based HW/SW co-designs, we present three different ASICs, designed since 2020, accelerating different subsets of the PQ-algorithms in the NIST com...     »