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Title:

A Hardware-based Multi-objective Thread Mapper for Tiled Manycore Architectures

Document type:
Konferenzbeitrag
Author(s):
Ravi Kumar Pujari, Thomas Wild, Andreas Herkersdorf
Abstract:
Thread mapping is typically performed as an integral part of cooperative or pre-emptive operating system (OS) scheduling in order to share the processor core(s) among competing applications. Schedulers usually follow a single-objective performance optimization, such as maximizing core utilization or satisfying deadlines by the prioritization of threads. Meeting multiple orthogonal objectives, like performance vs. power or thermal resilience, in the era of manycore processors is a challenge becau...     »
Keywords:
InvasIC B3
Dewey Decimal Classification:
620 Ingenieurwissenschaften
Book / Congress title:
33rd IEEE International Conference on Computer Design (ICCD)
Date of congress:
October 18-21
Year:
2015
Year / month:
2015-10
Month:
Oct
Pages:
459 - 462
Language:
en
Fulltext / DOI:
doi:10.1109/ICCD.2015.7357148
TUM Institution:
Lehrstuhl für Integrierte Systeme
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