An Efficient Hardware Architecture for Packet Re-sequencing in Network Processor MPSoCs

Title:: An Efficient Hardware Architecture for Packet Re-sequencing in Network Processor MPSoCs
Document type:: Konferenzbeitrag
Contribution type:: Textbeitrag / Aufsatz
Author(s):: Shadi Traboulsi, Michael Meitinger, Rainer Ohlendorf, Andreas Herkersdorf
Keywords:: FlexPath
Dewey Decimal Classification:: 620 Ingenieurwissenschaften
Book / Congress title:: 12th Euromicro Conference on Digital System Design (DSD)
Publisher address:: Patras, Greece
Year:: 2009
Year / month:: 2009-08
Month:: Aug
Language:: en
TUM Institution:: Lehrstuhl für Integrierte Systeme
Format:: Text
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