This paper presents an approach for modeling logic gates for the use in waveform-aware timing analysis. The model employs a symbolic system formulation which is derived from the SPICE netlist. Linear transfer functions deter- mine the port currents for applied port voltages. Their coefficients are functions of the port voltages to account for nonlinearities. Look-up tables are used to model this dependency. For characterizing the model only DC simu- lations are needed, making the model generation simple and fast. Only 75 seconds were needed to build an in- verter model on a standard desktop computer. Experimen- tal results are presented showing excellent agreement with SPICE simulation. Extensions for statistical application are outlined.      «

This paper presents an approach for modeling logic gates for the use in waveform-aware timing analysis. The model employs a symbolic system formulation which is derived from the SPICE netlist. Linear transfer functions deter- mine the port currents for applied port voltages. Their coefficients are functions of the port voltages to account for nonlinearities. Look-up tables are used to model this dependency. For characterizing the model only DC simu- lations are needed, making the model ge...     »