In this paper a probing detector consisting of digital gates is optimized. Probing attempt detectors are a solution for on-chip protection against probing of interconnects. They measure a wire and raise an alarm if an additional capacitance is recognized. The required additional circuitry for such detectors introduce area overhead. It copes with the tradeoff between low area overhead, low number of false alarms, and detectability of probes with very small capacitances. A simulation-based optimization of a specific probing detector architecture results in an improvement in probing sensitivity from 40fF to 20fF at low area overhead and with a low probability of false alarms.     «

In this paper a probing detector consisting of digital gates is optimized. Probing attempt detectors are a solution for on-chip protection against probing of interconnects. They measure a wire and raise an alarm if an additional capacitance is recognized. The required additional circuitry for such detectors introduce area overhead. It copes with the tradeoff between low area overhead, low number of false alarms, and detectability of probes with very small capacitances. A simulation-based optimi...     »