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Titel:

Side-Channel Leakage Aware Instruction Scheduling

Dokumenttyp:
Konferenzbeitrag
Art des Konferenzbeitrags:
Vortrag / Präsentation
Autor(en):
Seuschek, Hermann and Guillen, Oscar and De Santis, Fabrizio
Abstract:
Speed-optimized side-channel protected software implementations of block ciphers are important for the security of embedded IoT devices based on general-purpose microcontrollers. The recent work of Schwabe et al. published at SAC 2016 introduced a bit-sliced implementation of AES and a first-order Boolean-masked version of it, targeting ARM Cortex-M CPU cores. The authors claim to be secure against timing as well as first-order power and electromagnetic side-channel attacks. However, the auth...     »
Stichworte:
Side-Channel Countermeasures; Masking; Bit-sliced; Compilers
Dewey-Dezimalklassifikation:
620 Ingenieurwissenschaften
Kongress- / Buchtitel:
4th Workshop on Cryptography and Security in Computing Systems (CS2 2017) HIPEAC17
Kongress / Zusatzinformationen:
Stockholm, Sweden
Datum der Konferenz:
24.01.2017
Jahr:
2017
Quartal:
1. Quartal
Jahr / Monat:
2017-01
Monat:
Jan
Seiten:
Pages 7-12
Nachgewiesen in:
Web of Science
Print-ISBN:
978-1-4503-4869-0
Reviewed:
ja
Sprache:
en
Volltext / DOI:
doi:http://dx.doi.org/10.1145/3031836.3031838
WWW:
http://dl.acm.org/citation.cfm?id=3031838&CFID=910287680&CFTOKEN=27593222
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