This brief addresses the problem of implementing
very large constant multiplications by a single variable
under the shift-adds architecture using a minimum number
of adders/subtractors. Due to the intrinsic complexity of the
problem, we introduce an approximate algorithm, called TÕLL,
which partitions the very large constants into smaller ones. To
reduce the number of operations, TÕLL incorporates graph-based
and common subexpression elimination methods proposed for the
shift-adds design of constant multiplications. It can also consider
the delay of a multiplierless design defined in terms of the
maximum number of operations in series, i.e., the number of
adder-steps, while reducing the number of operations. High-level
experimental results show that the adder-steps of a shift-adds
design can be reduced significantly with a little overhead in the
number of operations. Gate-level experimental results indicate
that while the shift-adds design can lead to a 36.6% reduction
in gate-level area with respect to a design using a multiplier, the
delay-aware optimization can yield a 48.3% reduction in minimum
achievable delay of the shift-adds design when compared
to the area-aware optimization.
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This brief addresses the problem of implementing
very large constant multiplications by a single variable
under the shift-adds architecture using a minimum number
of adders/subtractors. Due to the intrinsic complexity of the
problem, we introduce an approximate algorithm, called TÕLL,
which partitions the very large constants into smaller ones. To
reduce the number of operations, TÕLL incorporates graph-based
and common subexpression elimination methods proposed for the
shift-adds design...
»