Knoth, Christoph;Schlichtmann, Ulf
Characterization of Standard Cells
93-106
Process Variations and Probabilistic Integrated Circuit Design
Dietrich, Manfred;Haase, Joachim
Springer
2012

Li, Bing;Schlichtmann, Ulf
Statistical Static Timing Analysis
117-126
Process Variations and Probabilistic Integrated Circuit Design
Dietrich, Manfred;Haase, Joachim
Springer
2012

Li, Bing;Schlichtmann, Ulf
Mathematical Modeling of Process Variations
81-88
Process Variations and Probabilistic Integrated Circuit Design
Dietrich, Manfred;Haase, Joachim
Springer
2012

Graeb, Helmut
From Sizing over Design Centering and Pareto Optimization to Tolerance Pareto Optimization of Electronic Circuits
35--38
Mathematics in Industry 16
Michielsen, B.;Poirier, J.-R.
Springer
2012

Knoth, Christoph;Jedda, Hela;Schlichtmann, Ulf
Current Source Modeling for Power and Timing Analysis at Different Supply Voltages
Design, Automation and Test in Europe (DATE)
2012

Todorov, Vladimir;Mueller-Gritschneder, Daniel;Reinig, Helmut;Schlichtmann, Ulf
Automated Construction of a Cycle-Approximate Transaction Level Model of a Memory Controller
Design, Automation and Test in Europe (DATE)
2012

Xu, Yang;Li, Bing;Hasholzner, Ralph;Rohfleisch, Bernhard;Haubelt, Christian;Teich, Jürgen
Variation-Aware Leakage Power Model Extraction for System-Level Hierarchical Power Analysis
Design, Automation and Test in Europe (DATE)
2012

Graeb, Helmut
ITRS 2011 Analog EDA Challenges and Approaches
Design, Automation and Test in Europe (DATE)
2012

Lu, Kun;Mueller-Gritschneder, Daniel;Schlichtmann, Ulf
Accurately Timed Transaction Level Models for Virtual Prototyping at High Abstraction Level
Design, Automation and Test in Europe (DATE)
2012

Chen, Qingqing;Csaba, György;Lugli, Paolo;Schlichtmann, Ulf;Rührmair, Ulrich
Characterization of the Bistable Ring PUF
Design, Automation and Test in Europe (DATE)
2012