User: Guest  Login
Title:

On the Efficiency of Design Time Evaluation of the Resistance to Power Attacks

Document type:
Konferenzbeitrag
Contribution type:
Textbeitrag / Aufsatz
Author(s):
Barenghi, A.; Bertoni, G.; De Santis, F.; Melzani, F.
Keywords:
circuit simulations; cryptographic algorithm; design time evaluation; design time power estimation tools; differential power attacks; fast feedback loops; power analysis attacks; security; side-channel attacks; cryptography
Book / Congress title:
Digital System Design (DSD), 2011 14th Euromicro Conference on
Congress (additional information):
Oulu, Finland
Year:
2011
Year / month:
2011-09
Month:
Sep
Pages:
777 -785
Reviewed:
ja
Language:
en
Fulltext / DOI:
doi:10.1109/DSD.2011.103
 BibTeX