Jones, Jefferson Parker;Van Kempen, Philipp;Mueller-Gritschneder, Daniel
Vicuna2.0: RISC-V Embedded Vector Unit with Half-Precision Floating-Point Support for TinyML
69-72
2025 Austrochip Workshop on Microelectronics (Austrochip)
IEEE
2025

Tahoori, Mehdi;Meyers, Vincent;Sadeghipour Roodsari, Mahboobe;Xu, Huashuangyang;Becker, Juergen;Harbaum, Tanja;Frombach, Felix;Hoefer, Julian;Sotiropoulos, Georgios;Henkel, Jorg;Demirdag, Zeynep;Khdr, Heba;Nassar, Hassan;Schlichtmann, Ulf;Geier, Johannes;van Kempen, Philipp;Sigl, Georg;Koegler, Stefan;Probst, Matthias;Teich, Jurgen;Hannig, Frank;Sabih, Muhammad;Sesli, Batuhan;Wehn, Norbert;Steiner, Lukas;Kunz, Wolfgang;Shelkamy Ali, Mohamed
Special Sessions - Hardware-Software Co-Design for Machine Learning Systems Made Open-Source
23-32
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis
ACM
2025

van Kempen, Philipp;Hager-Clukas, Andreas;Mueller-Gritschneder, Daniel;Schlichtmann, Ulf
GenIE: Reuse-Oriented Generation of Domain-Specific Instruction Extensions
1-7
2025 IEEE Nordic Circuits and Systems Conference (NorCAS)
IEEE
2025

Kappes, Johannes;Geier, Johannes;van Kempen, Phillipp;Mueller-Gritschneder, Daniel;Schlichtmann, Ulf
Automated Graph-level Passes for TinyML Fault Tolerance
1-9
2025 International Joint Conference on Neural Networks (IJCNN)
IEEE
2025

Zhao, Zhuorui;Li, Bing;Zhang, Grace Li;Schlichtmann, Ulf
VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning
IEEE International System-on-Chip Conference
2025

Zhao, Zhuorui;Qiu, Ruidi;Lin, Ing-Chao;Zhang, Grace Li;Li, Bing;Schlichtmann, Ulf
VRank: Enhancing Verilog Code Generation from Large Language Models via Self-Consistency
1-7
2025 26th International Symposium on Quality Electronic Design (ISQED)
IEEE
2025

Azevedo, Filipe;Leibl, Markus;Martins, Ricardo;Graeb, Helmut
Inverse Analog IC Sizing and Exploration through Diffusion Models and Structural Knowledge
2025 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design (SMACD)
2025

Schlamelcher, Jan;Goodfellow, Thomas;Kebianyor, Bewoayia;Nitsche, Gregor;Van Kempen, Philipp;Grüttner, Kim
Prototyping custom RISC-V instructions with Seal5 and CoreDSL
2025

Hager-Clukas, Andreas;van Kempen, Philipp;Wallentowitz, Stefan
ARISE: Automating RISC-V Instruction Set Extension
2025

Bellarmino, Nicolò;Cantoro, Riccardo;Huch, Martin;Kilian, Tobias;Schlichtmann, Ulf;Squillero, Giovanni
Deep Learning Strategies for Labeling and Accuracy Optimization in Microcontroller Performance Screening
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2025
44
2
641-654