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Title:

Integrated circuit including doped semiconductor line having conductive cladding

Document type:
Patent
Patent application number:
US 8084759 B2
Inventor:
KLOSTERMANN ULRICH ; SCHWERIN ULRIKE GRUENING-VON ; KREUPL FRANZ
Assignee:
KLOSTERMANN ULRICH ; SCHWERIN ULRIKE GRUENING-VON ; KREUPL FRANZ
Abstract:
An integrated circuit includes an array of memory cells and a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of memory cells. The integrated circuit includes conductive cladding contacting the doped semiconductor line.
Patent office:
US
Publication date patent:
27.12.2011
Year:
2011
Language:
en
TUM Institution:
Hybride Elektronische Systeme
Format:
Text
 BibTeX