Multi-core architectures could provide the computational power needed to the demanding hard real-time systems. However, the interference on the shared resources makes the Worst Case Execution Time (WCET) of applications running on a multi-core architecture impossible or hard to estimate.
Traditionally, predictable execution time is achieved after significantly sacrificing resource utilization/performance of the system. This thesis provides techniques that provide tight WCET bounds at minimal performance penalty.
Additionally, the timing aspect of the system stays in accordance with the CAST32 avionics certification guidelines.
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Multi-core architectures could provide the computational power needed to the demanding hard real-time systems. However, the interference on the shared resources makes the Worst Case Execution Time (WCET) of applications running on a multi-core architecture impossible or hard to estimate.
Traditionally, predictable execution time is achieved after significantly sacrificing resource utilization/performance of the system. This thesis provides techniques that provide tight WCET bounds at minimal pe...
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