HiPeC - High Performance Cryptographic Service for Heterogeneous Network-on-Chip Systems

We propose a high performance cryptographic co-processor integrated in a heterogeneous multicore system connected through a Network-on-Chip (NoC). Any general purpose processor (GPP) in the system can request cryptographic services by configuring the co-processor to perform en-/decryption using cryptography hardware. The co-processor is fully direct memory access (DMA) enabled, thus all connected components can utilize the en-/decryption functionality while copying data with DMA. In order to separate applications running on different GPPs through different keys, the co-processor features logically partitioned embedded key registers. The proposed approach addresses resistance against attackers which are capable of performing software attacks to obtain cryptographic keys from memory and snooping attacks on external interfaces like memory buses or network controllers. To our best knowledge, our solution is the first attempt to implement a cryptography co-processor for NoC systems offering complete functionality with integrated DMA, embedded key registers, command priority queues, and AES counter mode of operation (CTR) available as a service for all NoC components. The performance of our design is compared with a software-based approach. We demonstrate that the co-processor features over 230-times performance gain showing the value of this exible hardware based approach.     «

We propose a high performance cryptographic co-processor integrated in a heterogeneous multicore system connected through a Network-on-Chip (NoC). Any general purpose processor (GPP) in the system can request cryptographic services by configuring the co-processor to perform en-/decryption using cryptography hardware. The co-processor is fully direct memory access (DMA) enabled, thus all connected components can utilize the en-/decryption functionality while copying data with DMA. In order to se...     »