Post-quantum cryptography has emerged as a very attractive research
topic due to the recent advancements in the development of
quantum computers. Among the different available post-quantum
public-key algorithms, Supersingular Isogeny Key-Encapsulation
(SIKE) has posed a unique design challenge due to its resource intensive
arithmetic but is characterized by small key sizes. Existing
implementations of SIKE either focus on dedicated accelerators on
FPGA platforms or on assembly optimized software implementations
on ARM. A full FPGA implementation, though offering low
latency and high performance, suffers from the disadvantage of
having a large area footprint and a low flexibility. On the other
hand, a pure software implementation has lower performance compared
to FPGA implementations. In this paper, we propose hardware/
software co-design methodologies for SIKE and integrate a
redundant number based finite field accelerator into two microcontroller
platforms based on ARM and RISC-V. The result shows
that our implementation on ARM Cortex-A9 enhanced with a field
accelerator offers significant speedup in terms of clock cycles when
compared to standalone software implementations on ARM32 and
ARM64 . Moreover, to show how the communication overhead between
processor and accelerator can be mitigated, we integrated the
finite field accelerator directly into the core of a RISC-V processor.
To the best of our knowledge, this is the first design that applies
hardware/software co-design methodologies to implement SIKE on
ARM and RISC-V platforms. Our proposed design requires 65500 K
clock cycles to execute SIKEp434 on an ARM Cortex-A9 processor.
On RISC-V, our proposed design requires only 36900 K clock cycles.
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Post-quantum cryptography has emerged as a very attractive research
topic due to the recent advancements in the development of
quantum computers. Among the different available post-quantum
public-key algorithms, Supersingular Isogeny Key-Encapsulation
(SIKE) has posed a unique design challenge due to its resource intensive
arithmetic but is characterized by small key sizes. Existing
implementations of SIKE either focus on dedicated accelerators on
FPGA platforms or on assembly optimized s...
»