I present new fault emulation techniques for faults in combinational and sequential logic, which allow to model arbitrary fault attacks in industrial designs without performance loss compared to fault-free emulations. This enables efficient pre-silicon security verification. For instance, sophisticated attacks from multiple independent sources that may be time-displaced or overlap in time can be configured. To describe the configuration of arbitrary fault attacks, I introduce a fault configuration model.
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I present new fault emulation techniques for faults in combinational and sequential logic, which allow to model arbitrary fault attacks in industrial designs without performance loss compared to fault-free emulations. This enables efficient pre-silicon security verification. For instance, sophisticated attacks from multiple independent sources that may be time-displaced or overlap in time can be configured. To describe the configuration of arbitrary fault attacks, I introduce a fault configurati...
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