3D-ICs with through silicon vias (TSVs) allow multiplication of circuit capacities with constant area footprint. This dissertation covers the optimization of on-chip communication networks (NoCs) for 3D-ICs. A configurable circuit module for bundling vertical links to leverage physical properties of TSVs, like higher clocking of less RC loaded links is presented. With this approach, we could demonstrate a significant reduction of TSV induced area and achieved increased reliability. Furthermore, a synthesis algorithm for the automated generation of 3D-NoCs is outlined and researched.
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3D-ICs with through silicon vias (TSVs) allow multiplication of circuit capacities with constant area footprint. This dissertation covers the optimization of on-chip communication networks (NoCs) for 3D-ICs. A configurable circuit module for bundling vertical links to leverage physical properties of TSVs, like higher clocking of less RC loaded links is presented. With this approach, we could demonstrate a significant reduction of TSV induced area and achieved increased reliability. Furthermore,...
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