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Titel:

Timing Resilience for Efficient and Secure Circuits

Dokumenttyp:
Konferenzbeitrag
Autor(en):
Zhang, G. L. and Brunner, M. and Li, B. and Sigl, G.and Schlichtmann, U.
Seitenangaben Beitrag:
623-628
Abstract:
With recent advances in reverse engineering, attackers can reconstruct a netlist to counterfeit chips by opening the die and scanning all layers of authentic chips. This relatively easy counterfeiting is made possible by the use of the standard simple clocking scheme, where all combinational blocks function within one clock period, so that a netlist of combinational logic gates and flip-flops is sufficient to duplicate a design. In this paper, we propose to invalidate the assumption that a netl...     »
Dewey-Dezimalklassifikation:
620 Ingenieurwissenschaften
Kongress- / Buchtitel:
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC)
Kongress / Zusatzinformationen:
Beijing, China
Datum der Konferenz:
13.01.-16.01.2020
Jahr:
2020
Quartal:
1. Quartal
Jahr / Monat:
2020-01
Monat:
Jan
Seiten:
623-628
Reviewed:
ja
Sprache:
en
WWW:
https://aspdac2020.github.io/aspdac20/
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