Chou, Pang-Yen;Chen, Nai-Chen;Lin, Mark Po-Hung;Graeb, HelmutMatched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data ConvertersIEEE Transactions on Very Large Scale Integration Systems (TVLSI)2017
Zwerger, Michael;Neuner, Maximilian;Graeb, HelmutAnalog Power-Down SynthesisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems2017
Hu, Yong;Mueller-Gritschneder, Daniel;Schlichtmann, UlfA Model-based Framework For Networks-on-Chip Design Space Exploration2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS)2017jan
Wang, Qin;Zuo, Shiliang;Yao, Hailong;Ho, Tsung-Yi;Li, Bing;Schlichtmann, Ulf;Cai, YiciHamming-Distance-Based Valve-Switching Optimization for Control Multiplexing in Flow-Based Microfluidic Biochip (pdf)IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC)2017
Liu, Chunfeng;Li, Bing;Bhattacharya, Bhargab B.;Chakrabarty, Krishnendu;Ho, Tsung-Yi;Schlichtmann, UlfTesting Microfluidic Fully Programmable Valve Arrays (FPVAs) (pdf)Design, Automation and Test in Europe (DATE)2017
Chen, Nai-Chen;Chou, Pang-Yen;Graeb, Helmut;Lin, Mark Po-HungHigh-Density MOM Capacitor Array with Novel Mortise-Tenon Structure for Low-Power SAR ADCsDesign, Automation and Test in Europe (DATE)2017
Ibrahim, Mohamed;Chakrabarty, Krishnendu;Schlichtmann, UlfCoSyn: Efficient single-cell analysis using a hybrid microfluidic platformDesign, Automation & Test in Europe Conference & Exhibition (DATE)2017
Glocker, Elisabeth;Chen, Qingqing;Schlichtmann, Ulf;Landsiedel, Doris SchmittEmulation of an {ASIC} Power and Temperature Monitoring System (eTPMon) for {FPGA} PrototypingMicroprocessors and Microsystems201750may90--101
Martev, Dimo;Hampel, Sven;Schlichtmann, UlfMethodology for automated phase noise minimization in RF circuit interconnect treesIEEE International Symposium on Circuits and Systems (ISCAS)2017
Martev, Dimo;Hampel, Sven;Schlichtmann, UlfA Method for Phase Noise Analysis of RF CircuitsGreat Lakes Symposium on VLSI (GLVLSI)2017