{I}n situ measurement of aging-induced performance degradation in digital circuits
2016 21th IEEE European Test Symposium (ETS)
2016
{D}esign of an ultra-wideband low-noise amplifier for spin wave readout circuitry in 65 nm {CMOS} technology
2016 16th Mediterranean Microwave Symposium (MMS)
2016
{A} {P}arametric {L}ayout {S}tudy of {R}adiated {E}mission from {H}igh-{F}requency {H}alf-{B}ridge {S}witching {C}ells
CIPS 2016; 9th International Conference on Integrated Power Electronics Systems
2016
{A} 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm {CMOS} for time-mode {ADC}
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
2016
{A} 2 {GH}z 244 fs-{R}esolution 1.2 ps-{P}eak-{INL} {E}dge {I}nterpolator-{B}ased {D}igital-to-{T}ime {C}onverter in 28 nm {CMOS}
IEEE Journal of Solid-State Circuits
2016
51
12
Dec
2992-3004
{A} {S}implified {SPICE} {M}odel for {F}ast {P}arametric {O}ptimization of {H}igh {V}oltage {P}ower {E}lectronic {C}ircuits in the {M}egahertz {R}ange
CIPS 2016; 9th International Conference on Integrated Power Electronics Systems
2016
{C}haracterization of the magnetization reversal of perpendicular {N}anomagnetic {L}ogic clocked in the ns-range
AIP Advances
2016
6
5
{M}odeling and simulation of nanomagnetic logic with cadence virtuoso using {V}erilog-{A}
Solid-State Electronics
2016
-
{A} 2{GH}z 244fs-{R}esolution 1.2ps-{P}eak-{INL} {E}dge-{I}nterpolator-{B}ased {D}igital-to-{T}ime {C}onverter in 28nm {CMOS}
IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
2016
{T}est structures for {CMOS} {RF} reliability assessment
2016 International Conference on Microelectronic Test Structures (ICMTS)
2016