This work focuses on modeling and monitoring the impact of aging mechanisms on digital CMOS circuits. The impact of aging is determined in the design phase by a novel circuit level model. To monitor the aging mechanisms over lifetime and to predict upcoming failures, in situ monitors are introduced. Based on the monitor information, operating parameters like supply voltage and frequency are dynamically adjusted. Thus, oversized design guard-bands can be reduced, while high reliability requirements are ensured.
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This work focuses on modeling and monitoring the impact of aging mechanisms on digital CMOS circuits. The impact of aging is determined in the design phase by a novel circuit level model. To monitor the aging mechanisms over lifetime and to predict upcoming failures, in situ monitors are introduced. Based on the monitor information, operating parameters like supply voltage and frequency are dynamically adjusted. Thus, oversized design guard-bands can be reduced, while high reliability requiremen...
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