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Document type:
Konferenzbeitrag 
Contribution type:
Textbeitrag / Aufsatz 
Author(s):
Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf 
Title:
An architecture and an FPGA prototype of a Reliable Processor Pipeline towards multiple soft- and timing errors 
Keywords:
AiS 
Dewey Decimal Classification:
620 Ingenieurwissenschaften 
Book / Congress title:
14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems 
Year:
2011 
Year / month:
2011-04 
Month:
Apr 
Reviewed:
ja 
Language:
en 
TUM Institution:
Lehrstuhl für Integrierte Systeme 
Format:
Text