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Kimon Karras, Thomas Wild, Andreas Herkersdorf
A Folded Pipeline Network Processor Architecture for 100 Gbit/s Networks
ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS)
2010
Lothar Stolz, Holger Endt, Mikael Vaaraniemi, Daniel Zehe, Walter Stechele
Energy consumption of Graphic Processing Units with respect to automotive use-cases
International Conference on Energy Aware Computing (ICEAC)
2010
Florian Aschauer, Christopher Claus, Walter Stechele
In-flight verification of CCSDS based on-board real-time video compression
61. International Astronautical Congress (IAC)
2010
Michael Feilen, Matthias Ihmig, Walter Stechele
Concept and Design of an SNR-adaptive DRM+/FM Receiver using Dynamic Partial Reconfiguration (DPR) of FPGAs
11th Workshop Digital Broadcasting
2010
Walter Stechele, Christopher Claus, Andreas Laika
Lessons Learned from last 4 Years of Reconfigurable Computing
Dagstuhl Seminar Proceedings 10281 on Dynamically Reconfigurable Architectures
2010
Andreas Laika, Johny Paul, Christopher Claus, Walter Stechele, Adam El Sayed Auf, Erik Maehle
FPGA-based Real-time Moving Object Detection for Walking Robots
8th IEEE International Workshop on Safety, Security and Rescue Robotics (SSRR)
2010
Roman Plyaskin, Alejandro Masrur, Martin Geier, Samarjit Chakraborty, Andreas Herkersdorf
High-level timing analysis of concurrent applications on MPSoC platforms using memory-aware trace-driven simulations
18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC)
2010
Andreas Bernauer, Johannes Zeppenfeld, Oliver Bringmann, Andreas Herkersdorf, Wolfgang Rosenstiel
Combining software and hardware LCS for lightweight on-chip learning
3rd IFIP Conference on Biologically-Inspired Collaborative Computing
2010
Andreas Herkersdorf, Andreas Lankes, Michael Meitinger, Rainer Ohlendorf, Stefan Wallentowitz, Thomas Wild, Johannes Zeppenfeld
Hardware Support to Exploit Parallelism in Homogeneous and Heterogeneous Multi-Core Systems on Chip
Springer Verlag
2010
Robert Hartl, Andreas Rohatschek, Walter Stechele, Andreas Herkersdorf
Architectural Vulnerability Factor Estimation with Backwards Analysis
13th Euromicro Conference on Digital System Design (DSD)
2010
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