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EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration under Process Variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2018
Quality Assessment of Generated Hardware Designs Using Statistical Analysis and Machine Learning
International Conference on Tools with Artificial Intelligence (ICTAI)
2018
Analog Fault Simulation Automation at Schematic Level with Random Sampling Techniques
International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)
2018
Meta-model Based Automation of Properties for Pre-Silicon Verification
IFIP International Conference on Very Large Scale Integration (VLSI)
2018
An Efficient Fault-Tolerant Valve-Based Microfluidic Routing Fabric for Single-Cell Analysis
IEEE European Test Symposium
2018
A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications
EUROMICRO Conference on Digital System Design (DSD)
2018
Synthesis of Decoder Tables using Formal Verification Tools
Design and Verification Conference and Exhibition (DVCon)
2018
On Enabling Diagnosis for 1-Pin Test Fails in an Industrial Flow
Asia and South Pacific Design Automation Conference (ASP-DAC)
2018
From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era
IPSJ Transactions on System LSI Design Methodology
2018
11
feb
2-15
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2018
37
2
feb
392--405