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{Optimization of Transient-Fault Injection Through Analysis of Simulation Traces}
edaWorkshop
2016
1--6
{Speeding up Safety Verification by Fault Abstraction and Simulation to Transaction Level}
IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)
2016
1--6
{Fault-Effect Analysis on System-Level Hardware Modeling using Virtual Prototypes}
Forum on Specification and Design Languages (FDL)
2016
1--7
{Gate-Level-Accurate Fault-Effect Analysis at Virtual-Prototype Speed}
ERCIM/EWICS/ARTEMIS Workshop on ``Dependable Embedded and Cyber-physical Systems and Systems-of-Systems'' (DECSoS'16)
2016
1--13
{Efficient Checkpointing-Based Safety-Verification Flow Using Compiled-Code Simulation}
Digital System Design (DSD), 2016 Euromicro Conference on
2016
1--8
{Fault-Effect Analysis on Multiple Abstraction Levels in Hardware Modeling}
DVCon USA
2016
1--12
{Safety-Verification Flow Sporting Gate-Level Accuracy and Near Virtual-Prototype Speed}
DVCon Europe
2016
1--8
A Step-Accurate Model for the Trapping and Release of Charge Carriers Suitable for the Transient Simulation of Analog Circuits
Journal of Microelectronics Reliability
2016
Design centric modeling of digital hardware
High Level Design Validation and Test Workshop (HLDVT), 2016 IEEE International
2016
Transformation of Failure Propagation Models into Fault Trees for Safety Evaluation Purposes
Dependable Systems and Networks Workshop, 2016 46th Annual IEEE/IFIP International Conference on
2016