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- Title:
{A} 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm {CMOS} for time-mode {ADC}
- Author(s):
- Kong, J.; Henzler, S.; Schmitt-Landsiedel, D.; Siek, L.
- Keywords:
- Computer architecture; Delays; Dynamic range; Logic gates; Microprocessors; Quantization (signal); Signal resolution; Time-to-digital Converter (TDC); body-biasing; time-mode ADC; two-step architecture; vernier TDC
- Book / Congress title:
- 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
- Year:
- 2016
- Month:
- Oct
- Pages:
- 348-351
- Fulltext / DOI:
- doi:10.1109/APCCAS.2016.7803972
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