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Document type:
Konferenzbeitrag 
Author(s):
Brunner, M. and Baehr, J. and Sigl, G. 
Title:
Improving on State Register Identification in Sequential Hardware Reverse Engineering 
Abstract:
In the past years, new hardware reverse engineering methods for sequential gate-level netlists have been developed to detect Hardware Trojans and counteract Design Piracy. A critical part of sequential gate-level netlist reverse engineering is the identification of state registers. A promising method to solve this problem, RELIC, proposed by T. Meade et al., is based on input structure similarities of registers to differentiate between state and non-state registers. We propose an improvement to...    »
 
Keywords:
Registers; Logic gates; Reverse engineering; Hardware; Heuristic algorithms; Complexity theory; Clocks; Hardware Reverse Engineering; Sequential Reverse Engineering; State Register Identification; FSM Extraction 
Dewey Decimal Classification:
620 Ingenieurwissenschaften 
Book / Congress title:
2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) 
Congress (additional information):
Washington, D.C., USA 
Year:
2019 
Quarter:
2. Quartal 
Year / month:
2019-05 
Month:
May 
Pages:
151-160 
Fulltext / DOI: