HW-Flow-Fusion: Inter-Layer Scheduling for Convolutional Neural Network Accelerators with Dataflow Architectures

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Title:: HW-Flow-Fusion: Inter-Layer Scheduling for Convolutional Neural Network Accelerators with Dataflow Architectures
Document type:: Zeitschriftenaufsatz
Author(s):: Valpreda, Emanuele ; Morì, Pierpaolo ; Fasfous, Nael ; Vemparala, Manoj Rohit ; Frickenstein, Alexander ; Frickenstein, Lukas ; Stechele, Walter ; Passerone, Claudio ; Masera, Guido ; Martina, Maurizio
Keywords:: Article ; DNN ; layer-fusion ; scheduling ; accelerator ; dataflow ; memory hierarchy
Journal title:: Electronics
Year:: 2022
Journal volume:: 11
Journal issue:: 18
Fulltext / DOI:: doi:10.3390/electronics11182933
Publisher:: MDPI
E-ISSN:: 2079-9292
Date of publication:: 16.09.2022
CC license:: by, https://creativecommons.org/licenses/by/4.0

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