Cache Management and Time-triggered Scheduling for Hard Real-time MPSoCs

In hard real-time MPSoCs, shared cache has been considered as one of the major factors that degrade system predictability. How to manage the shared cache in order to optimize the system performance while guaranteeing the system predictability is still an open issue. State-of-the-art techniques on this topic use page coloring to partition the shared cache at OS level. In this paper, we present a cache management framework for hard real-time MPSoCs. The framework supports way-based cache partitioning at hardware level, building task-level time-triggered reconfigurable-cache MPSoCs. We evaluated the proposed framework w.r.t. different numbers of cores and cache modules and prototyped the constructed MPSoCs on FPGA. Experiment results based on FPGA measurements demonstrate the effectiveness of the proposed framework.     «

In hard real-time MPSoCs, shared cache has been considered as one of the major factors that degrade system predictability. How to manage the shared cache in order to optimize the system performance while guaranteeing the system predictability is still an open issue. State-of-the-art techniques on this topic use page coloring to partition the shared cache at OS level. In this paper, we present a cache management framework for hard real-time MPSoCs. The framework supports way-based cache partitio...     »