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Chou, Pang-Yen;Chen, Nai-Chen;Lin, Mark Po-Hung;Graeb, Helmut
Matched-Routing Common-Centroid 3-D MOM Capacitors for Low-Power Data Converters
IEEE Transactions on Very Large Scale Integration Systems (TVLSI)
2017
Zwerger, Michael;Neuner, Maximilian;Graeb, Helmut
Analog Power-Down Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2017
Hu, Yong;Mueller-Gritschneder, Daniel;Schlichtmann, Ulf
A Model-based Framework For Networks-on-Chip Design Space Exploration
2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS)
2017
jan
Chen, Nai-Chen;Chou, Pang-Yen;Graeb, Helmut;Lin, Mark Po-Hung
High-Density MOM Capacitor Array with Novel Mortise-Tenon Structure for Low-Power SAR ADCs
Design, Automation and Test in Europe (DATE)
2017
Ibrahim, Mohamed;Chakrabarty, Krishnendu;Schlichtmann, Ulf
CoSyn: Efficient single-cell analysis using a hybrid microfluidic platform
Design, Automation & Test in Europe Conference & Exhibition (DATE)
2017
Glocker, Elisabeth;Chen, Qingqing;Schlichtmann, Ulf;Landsiedel, Doris Schmitt
Emulation of an {ASIC} Power and Temperature Monitoring System (eTPMon) for {FPGA} Prototyping
Microprocessors and Microsystems
2017
50
may
90--101
Martev, Dimo;Hampel, Sven;Schlichtmann, Ulf
Methodology for automated phase noise minimization in RF circuit interconnect trees
IEEE International Symposium on Circuits and Systems (ISCAS)
2017
Martev, Dimo;Hampel, Sven;Schlichtmann, Ulf
A Method for Phase Noise Analysis of RF Circuits
Great Lakes Symposium on VLSI (GLVLSI)
2017
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