This paper describes a demultiplexer combined with a clock regenerator for 1 Gbit/s PCM signals. The demultiplexer divides the incoming signal into four parallel 250 Mbit/s channels using fast hybrid integrated ECL-gates with rise time of less than 400 ps. All clock signals needed to drive these gates are extracted from the input signal by a phase locked loop using two frequency doubler stages between the local oscillator and the phase detector. Since the logic levels and supply voltages of the hybrid integrated ECL-gates are fully compatible with those of monolithic integrated ECL circuits, such ECL-circuits can be directly connected to the outputs of the demultiplexer.     «

This paper describes a demultiplexer combined with a clock regenerator for 1 Gbit/s PCM signals. The demultiplexer divides the incoming signal into four parallel 250 Mbit/s channels using fast hybrid integrated ECL-gates with rise time of less than 400 ps. All clock signals needed to drive these gates are extracted from the input signal by a phase locked loop using two frequency doubler stages between the local oscillator and the phase detector. Since the logic levels and supply voltages of the...     »