Chip-to-Chip and On-Chip Communications

Radio frequency engineering aspects involved in wired and wireless interconnects are investigated first. There is a multitude of requirements for chip-to-chip communication, which an integrated antenna has to fulfill, like large bandwidth, small geometrical profile, and so on. Therefore, a detailed study of the possible solutions for an integrated on-chip antenna is performed. Novel solutions, which make use of the digital circuit's ground plane as a radiating element, are investigated. In the third section, the signal processing and coding aspects involved are carried out based on the obtained channel models, where both multiconductor interconnects and wireless multiantenna interconnects are interpreted as discrete-time, multi-input-multi-output (MIMO) systems. In the last section of this chapter appropriate silicon area, timing, and energy cost models for high-throughput LDPC decoders, which reproduce accurately the non-linear dependencies and being applicable to bit-parallel as well as to bit-serial decoder architectures are presented. These models allow for a quantitative comparison of different decoder architectures revealing the most area and energy efficient architecture for a given code and throughput specification. Additionally, a new highly area and energy efficient architecture based on a bit-serial interconnect is derived. This architecture is the result of a systematic architecture search and proper optimization based on the cost models.     «

Radio frequency engineering aspects involved in wired and wireless interconnects are investigated first. There is a multitude of requirements for chip-to-chip communication, which an integrated antenna has to fulfill, like large bandwidth, small geometrical profile, and so on. Therefore, a detailed study of the possible solutions for an integrated on-chip antenna is performed. Novel solutions, which make use of the digital circuit's ground plane as a radiating element, are investigated. In the t...     »