The growing demand of processing power in an increasing number of embedded systems deployed in various circumstances has led to new challenges towards the development of such systems. One of these challenges is a digital system's resiliency against soft errors that can alter internal states and lead to unforeseen and sometimes critical behavior. Simulating such errors at a system's early design phases can help with integrating and evaluating countermeasures. This work introduces a fast Register Transfer Level (RTL)-based fault injection framework for soft-error evaluations of RISC-V processor cores. To enable injections, a tool was developed that transforms the RTL model and builds a specific injection Application Programming Interface (API) from the core's hardware description. The modified RTL and built API were put to test in a proof of concept framework evaluating an open-hardware RISC-V core's behavior towards random bit flips in its internal states. The framework is characterized by its utilization of automatically generated, however, core-specific sources which enable a high fault injection capability while maintaining low simulation overhead. The evaluation results were analyzed with respect to the probability of a certain error occurring after a random bit flip and the probability of a specific injection target being the cause for a certain error.     «

The growing demand of processing power in an increasing number of embedded systems deployed in various circumstances has led to new challenges towards the development of such systems. One of these challenges is a digital system's resiliency against soft errors that can alter internal states and lead to unforeseen and sometimes critical behavior. Simulating such errors at a system's early design phases can help with integrating and evaluating countermeasures. This work introduces a fast Registe...     »

The growing demand of processing power in an increasing number of embedded systems deployed in various circumstances has led to new challenges towards the development of such systems. One of these challenges is a digital system's resiliency against soft errors that can alter internal states and lead to unforeseen and sometimes critical behavior. Simulating such errors at a system's early design phases can help with integrating and evaluating countermeasures. This work introduces a fast Register Transfer Level (RTL)-based fault injection framework for soft-error evaluations of RISC-V processor cores. To enable injections, a tool was developed that transforms the RTL model and builds a specific injection Application Programming Interface (API) from the core's hardware description. The modified RTL and built API were put to test in a proof of concept framework evaluating an open-hardware RISC-V core's behavior towards random bit flips in its internal states. The framework is characterized by its utilization of automatically generated, however, core-specific sources which enable a high fault injection capability while maintaining low simulation overhead. The evaluation results were analyzed with respect to the probability of a certain error occurring after a random bit flip and the probability of a specific injection target being the cause for a certain error.     «

The growing demand of processing power in an increasing number of embedded systems deployed in various circumstances has led to new challenges towards the development of such systems. One of these challenges is a digital system's resiliency against soft errors that can alter internal states and lead to unforeseen and sometimes critical behavior. Simulating such errors at a system's early design phases can help with integrating and evaluating countermeasures. This work introduces a fast Registe...     »