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Zhang, Li;Li, Bing;Shi, Yiyu;Hu, Jiang;Schlichtmann, Ulf
EffiTest2: Efficient Delay Test and Prediction for Post-Silicon Clock Skew Configuration under Process Variations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2018
Servadei, Lorenzo;Zennaro, Elena;Devarajegowda, Keerthikumara;Ecker, Wolfgang;Wille, Robert
Quality Assessment of Generated Hardware Designs Using Statistical Analysis and Machine Learning
International Conference on Tools with Artificial Intelligence (ICTAI)
2018
Wu, Liang;Hussain, Mohammad Khizer;Abughannam, Saed;Müller, Wolfgang;Scheytt, Christoph;Ecker, Wolfgang
Analog Fault Simulation Automation at Schematic Level with Random Sampling Techniques
International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)
2018
Devarajegowda, Keerthikumara;Ecker, Wolfgang
Meta-model Based Automation of Properties for Pre-Silicon Verification
IFIP International Conference on Very Large Scale Integration (VLSI)
2018
Moradi, Yasamin;Chakrabarty, Krishnendu;Schlichtmann, Ulf
An Efficient Fault-Tolerant Valve-Based Microfluidic Routing Fabric for Single-Cell Analysis
IEEE European Test Symposium
2018
Zennaro, Elena;Servadei, Lorenzo;Devarajegowda, Keerthikumara;Ecker, Wolfgang
A Machine Learning Approach for Area Prediction of Hardware Designs from Abstract Specifications
EUROMICRO Conference on Digital System Design (DSD)
2018
Devarajegowda, Keerthikumara;Schreiner, Johannes;Ecker, Wolfgang
Synthesis of Decoder Tables using Formal Verification Tools
Design and Verification Conference and Exhibition (DVCon)
2018
Tille, Daniel;Gottinger, Benedikt;Pfannkuchen, Ulrike;Graeb, Helmut;Schlichtmann, Ulf
On Enabling Diagnosis for 1-Pin Test Fails in an Industrial Flow
Asia and South Pacific Design Automation Conference (ASP-DAC)
2018
Li, Bing;Hashimoto, Masanori;Schlichtmann, Ulf
From Process Variations to Reliability: A Survey of Timing of Digital Circuits in the Nanometer Era
IPSJ Transactions on System LSI Design Methodology
2018
11
feb
2-15
Zhang, Li;Li, Bing;Liu, Jinglan;Shi, Yiyu;Schlichtmann, Ulf
Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2018
37
2
feb
392--405
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