Integrated circuit including doped semiconductor line having conductive cladding
Document type:
Patent
Patent application number:
US 8084759 B2
Inventor:
KLOSTERMANN ULRICH ; SCHWERIN ULRIKE GRUENING-VON ; KREUPL FRANZ
Assignee:
KLOSTERMANN ULRICH ; SCHWERIN ULRIKE GRUENING-VON ; KREUPL FRANZ
Abstract:
An integrated circuit includes an array of memory cells and a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of memory cells. The integrated circuit includes conductive cladding contacting the doped semiconductor line.