The reliability of analog integrated circuits becomes a major concern for the semiconductor industry as technology continuously scales. This thesis proposes an efficient method for sizing of analog integrated circuits towards the robustness in their lifetime. It is based on the analysis and optimization of the fresh worst-case distance value for each circuit performance as a robustness measure considering manufacturing process variations and transistor aging effects. The fresh and aged sizing rules and the maximum area constraints are checked during the optimization. The trade-off between the circuit lifetime and the price we pay in terms of layout area is studied in detail. To further speedup the lifetime robustness prediction, the thesis establishes a new framework to estimate the aged worst-case distance values based on sensitivity analyses of the fresh circuit.     «

The reliability of analog integrated circuits becomes a major concern for the semiconductor industry as technology continuously scales. This thesis proposes an efficient method for sizing of analog integrated circuits towards the robustness in their lifetime. It is based on the analysis and optimization of the fresh worst-case distance value for each circuit performance as a robustness measure considering manufacturing process variations and transistor aging effects. The fresh and aged sizing ru...     »