This thesis describes all steps to place the modules (e.g., standard cell or macro cells) of an integrated circuit on a given chip area. During global placement, a novel net model is used to express the linear netlength accurately in the quadratic objective function. In addition, two forces are integrated in the objective function such that the convergence of the global placement algorithm is assured. To optimize the routability of the circuit, a new approach for congestion estimation is presented and integrated in the placement algorithm. During legalization, the remaining module overlap is removed. For this purpose, two new approaches are described, and both minimize the quadratic movement of the modules. The first approach is suitable for standard cell circuits and the second one is suitable for macro cell circuits.
«
This thesis describes all steps to place the modules (e.g., standard cell or macro cells) of an integrated circuit on a given chip area. During global placement, a novel net model is used to express the linear netlength accurately in the quadratic objective function. In addition, two forces are integrated in the objective function such that the convergence of the global placement algorithm is assured. To optimize the routability of the circuit, a new approach for congestion estimation is present...
»