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Document type:
Technical Report 
Author(s):
Norbert Froehlich; Rolf Schlagenhaft; Josef Fleischmann 
Title:
Partitioning VLSI-Circuits for Parallel Simulation on Transistor Level 
Abstract:
For parallel simulation of VLSI circuits on transistor level a sophisticated partitioning of the circuits into subcircuits is crucial. Each net connecting the subcircuits causes additional communication and computation effort. As the slave processors simulating the subcircuits advance synchronously in time, the computation effort for each subcircuit should be approximately the same. In this paper we present a new approach for partitioning VLSI circuits on transistor level yielding a low number o...    »
 
Keywords:
partitioning on transistor level; parallel analogous simulation 
Year:
1997 
Year / month:
1997-04-01 00:00:00 
Pages:
18 Pages