This paper demonstrates a Fault Attack on an AES core protected by an infection type countermeasure. The redundant AES is implemented on a Xilinx Spartan-6 FPGA, with a feature size of 45 nm. By injecting exactly the same fault in both state registers of the redundant implementation using lasers, we are able to annul the protection added by the countermeasure and thus perform a successful Differential Fault Analysis. This requires a high precision double laser setup in order to hit two different locations on the chip at the same point in time. With a priori knowledge about the location of both state registers, we were able to generate applicable faulty ciphertexts within minutes. Our results show that for applications demanding a high level of security, relying on a duplication of hardware is not sufficient.     «

This paper demonstrates a Fault Attack on an AES core protected by an infection type countermeasure. The redundant AES is implemented on a Xilinx Spartan-6 FPGA, with a feature size of 45 nm. By injecting exactly the same fault in both state registers of the redundant implementation using lasers, we are able to annul the protection added by the countermeasure and thus perform a successful Differential Fault Analysis. This requires a high precision double laser setup in order to hit two different...     »