EGIS NoC: A secure-enhanced interconnection to prevent Architectural Channel Attacks

Logical Side Channel Attacks (SCAs) became a relevant threat for Multi-Processors System-on-Chips (MPSoCs). They are able to remotely and without being noticed to extract sensitive information from the timing behaviour of the MPSoC. Despite previous works have proposed MPSoCs architectures to mitigate some of the SCAs which arise from sharing memory and processor resources, the communication structure is still unprotected and leaking information. In this work, we propose EGIS NoC, a Network-on-Chip for MPSoCs capable to avoid several known SCAs. EGIS employs three main strategies to transparently protect sensitive applications: i) Dual switching mode; ii) Timing Noise insertion; and iii) Trust engine. EGIS security and performance were evaluated under different attack and performance benchmarks. Performance results of EGIS are acceptable, being dependent of the security level. Moreover, EGIS presents a low area and power overhead, being feasible to use our solution for constrained resource systems.     «

Logical Side Channel Attacks (SCAs) became a relevant threat for Multi-Processors System-on-Chips (MPSoCs). They are able to remotely and without being noticed to extract sensitive information from the timing behaviour of the MPSoC. Despite previous works have proposed MPSoCs architectures to mitigate some of the SCAs which arise from sharing memory and processor resources, the communication structure is still unprotected and leaking information. In this work, we propose EGIS NoC, a Network-...     »