Multi-Processors Systems-on-Chip (MPSoCs), as a key technology enabler of the new computation paradigm Internet-of-Things (IoT), are exposed to attacks. Malicious applications can be downloaded at runtime to the MPSoC, infect IPs and open doors to perform timing attacks. By monitoring the Network-on-Chip (NoC) traffic, an attacker is able to spy sensitive information such as secret keys. Previous works have shown that NoC routers can be used to avoid timing attacks. However, such approaches may lead to overall system performance degradation. In this paper we propose SER, a secure enhanced router architecture that dynamically configures the router memory space according to the communication and security properties of the traffic. Timing attacks are avoided by turning the attacker oblivious of the sensitive traffic. We evaluate the security, performance and cost of our approach. We show that our architecture is able to secure paths during runtime while adding only low cost and performance penalties to the MPSoC.     «

Multi-Processors Systems-on-Chip (MPSoCs), as a key technology enabler of the new computation paradigm Internet-of-Things (IoT), are exposed to attacks. Malicious applications can be downloaded at runtime to the MPSoC, infect IPs and open doors to perform timing attacks. By monitoring the Network-on-Chip (NoC) traffic, an attacker is able to spy sensitive information such as secret keys. Previous works have shown that NoC routers can be used to avoid timing attacks. However, such approaches...     »