User: Guest  Login
Author(s):
Li, Y.; Schneider, H.; Schnabel, F.; Thewes, R.; Schmitt-Landsiedel, D. 
Title:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation 
Pages contribution:
126-135 
Chapter contribution:
Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization 
Book title:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Proceedings 
Publisher:
Springer-Verlag 
Publisher address:
Berlin, Heidelberg 
Year:
2009