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- Autor(en):
- Li, Y.; Schneider, H.; Schnabel, F.; Thewes, R.; Schmitt-Landsiedel, D.
- Titel:
- Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
- Seitenangaben Beitrag:
- 126-135
- Kapitel Beitrag:
- Latched CMOS DRAM Sense Amplifier Yield Analysis and Optimization
- Buchtitel:
- Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008, Proceedings
- Verlag / Institution:
- Springer-Verlag
- Verlagsort:
- Berlin, Heidelberg
- Jahr:
- 2009
- DOI:
- doi:10.1007/978-3-540-95948-9
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