Many methods for analog circuit sizing are available as commercial, in-house and academic tools. They are based on continuous optimization, e.g., of transistor geometries, although the subsequent layout step requires values on a pre-defined grid. In addition, sizing of transistors for bipolar and RF circuits frequently necessitates the use of multiples of predefined values for the design parameters. This paper presents a novel method for solving this type of discrete optimization problem. An iterative approach is presented, which is based on pseudo-gradients and a randomized calculation of search regions and steps. Experimental comparisons with simulated annealing and a continuous sizing approach with subsequent discretization clearly show the effectivity and efficiency of the presented method.     «

Many methods for analog circuit sizing are available as commercial, in-house and academic tools. They are based on continuous optimization, e.g., of transistor geometries, although the subsequent layout step requires values on a pre-defined grid. In addition, sizing of transistors for bipolar and RF circuits frequently necessitates the use of multiples of predefined values for the design parameters. This paper presents a novel method for solving this type of discrete optimization problem. An it...     »