Benutzer: Gast  Login
Originaltitel:
Low-Frequency-Noise Reduction Technique for Linear Analog CMOS IC's 
Übersetzter Titel:
Ein neues Verfahren zur Reduktion des niederfrequenten Rauschens in linearen analogen CMOS Schaltungen 
Jahr:
2005 
Dokumenttyp:
Dissertation 
Institution:
Fakultät für Elektrotechnik und Informationstechnik 
Betreuer:
Brederlow, Ralf (Dr.) 
Gutachter:
Schmitt-Landsiedel, Doris (Prof. Dr.); Klar, Heinrich (Prof. Dr.) 
Format:
Text 
Sprache:
en 
Fachgebiet:
ELT Elektrotechnik 
Kurzfassung:
For AMS (analog-mixed signal) and RF (radio frequency) implementations CMOS (Complementary Metal Oxide Semiconductor) technology platforms are the mainstream today. These platforms provide great density and power savings on digital parts on the same chip and, in addition, a good mix of components for analog design. The analog performance of CMOS technology is worse compared to other technology options (e.g. bipolar technology), and its major advantage is the lower total cost of system. Several drawbacks have to overcome to build high performance analog integrated circuits using CMOS technology. One of those drawbacks is the poor 1/f noise property of CMOS technology.
Recently, but about ten years after this effect was first reported by Bloom and Nemirovsky of Technion-Israel Institute of Technology in Israel, the AMS/RF engineers began to pay an attention to a device-physics related effect: the periodical on-off switching of a MOSFET between strong inversion and accumulation leads to an anomalous reduction of the intrinsic 1/f noise of those devices. Especially, B. Nauta’s group of Twente University in the Netherlands has been exploring its feasibility in a large signal circuits like VCO’s. Although they seem to be the first to make use of the device-physics for the “real engineering world,” they have not fully exploited the advantage of it. Direct use of the effect based on their evaluations is only feasible for a limited amount of circuits, where a bias current is needed only during certain time intervals or where signal processing is not taking place continuously.
The aim of this thesis is to present and to develop a principle for the 1/f noise reduction in linear analog CMOS IC’s, using the known device physics-based effect which is aimed to be used in all kind of circuits including linear and time continuous circuits. This thesis describes the mathematical modeling, physical implementation and experimental demonstration of the principle in the fulfillment of this aim. In a first step, we propose the principle, “the complementary switched MOSFET architecture.” Then, as an application example for the principle, we investigate an operational amplifier architecture which includes the principle. It is modified from a two-stage CMOS miller operational amplifier and later compared to a classical design of that class.
The principle is experimentally demonstrated in a standard 0.12 µm, 1.5 V digital CMOS technology and a threefold reduction (5dB) of the 1/f noise is achieved at 10 Hz compared to a reference circuit. The impact of the circuit performances is minor – e.g., a slight increase (6%) of the power-consumption, a slight degradation (1dB DC gain) of the open-loop ac characteristics and no significant change in the linearity (THD) of the architecture. The switching glitches, which originate from the principle, are easily suppressed by a first order low pass filter. In addition, the property of the 1/f noise reduction principle is investigated under various clock frequencies and off-voltages. Furthermore, the mathematical descriptions for the noise behavior and the signal transfer of the proposed operational amplifier architecture are derived. With the help of the derived equations, the distinct features of the principle are identified from the measurements and simulations: the noise aliasing due to the principle and the increase in the white noise plateau which attributes to thermal resistive noise increase of the switches with increasing clock frequency. Finally, it is noted that the clock mismatch parameter tp should be optimized for best electrical performance.
The proposed principle is more area-effective compared to the most simple 1/f noise reduction method, the increase of an active area of noisy transistors. A twofold area increase of a transistor only leads to a factor of two in reduction of its 1/f noise, but the proposed circuit implementations yields a factor of three. This reduction factor is further enhanced to six with a proper noise-care design approach. Compared to the standard industry approach of chopper stabilization for 1/f noise reduction, less energetic glitches arise and thus less glitches have to be suppressed avoiding a higher order low pass filters which increases the complexity of circuits. Compared to the technique of correlated double sampling, the same increase in the white noise plateau is observed. This technique finds its main application in a discrete signal processing system like sampled-data or sample and hold circuits, so that the use of this technique to a continuous signal processing system is reluctant.
Results from this work should give a good guideline to AMS/RF circuit designers on how to best implement the noise reduction principle into their circuits. 
Übersetzte Kurzfassung:
Die Dissertation untersucht ein neues Verfahren zur Reduktion des niederfrequenten Rauschens in linearen analogen CMOS Schaltungen. MOSFETs, welche periodisch zwischen Akkumulation und Inversion geschaltet werden, zeigen ein gegenüber konstanten Arbeitspunkten reduziertes 1/f-Rauschen. Unter Ausnutzung dieses physikalischen Effektes wird mit Hilfe im Rahmen der Dissertation entwickelter Schaltungstechnik eine Unterdrückung der Rauschleistung von bis zu 8dB erreicht. Die Auswirkungen der dazu not...    »
 
Veröffentlichung:
Universitätsbibliothek der Technischen Universität München 
Mündliche Prüfung:
01.12.2005 
Dateigröße:
2196218 bytes 
Seiten:
113 
Letzte Änderung:
25.06.2007