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Matthias Ihmig, Andreas Herkersdorf
Flexible multi-standard multi-channel system architecture for Software Defined Radio receiver
Intelligent Transport Systems Telecommunications (ITST), The 9th International Conference on ITS Telecommunications
2009

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Paul Zuber, Othman Bahlous, Thomas Ilnseher, Michael Ritter, Walter Stechele
Wire Topology Optimization for Low Power CMOS
1-11
Very Large Scale Integration (VLSI) Systems, IEEE Transactions
2009

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Abdelmajid Bouajila, Johannes Zeppenfeld, Andreas Herkersdorf, Walter Stechele
Multi-Bit Error Protection for Self-Correcting CPU Pipelines
eda Workshop
2009

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Abelmajid Bouajila, Thomas Sommer, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf
A Fault-Tolerant Processor Architecture
Workshop „Dependability and Fault-Tolerance“ (ARCS)
2009

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Daniel Llorente, Kimon Karras, Thomas Wild, Andreas Herkersdorf
Advanced Packet Segmentation and Buffering Algorithms in Network Processors
4th International Conference on High Performance and Embedded Architectures and Compilers
2009

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Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf
FlexPath NP- Flexible, Dynamically Reconfigurable Processing Paths in Network Processors
Dynamically Reconfigurable Systems, Architectures, Design, Methods and Applications
Springer
2009

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Andreas Lankes, Andreas Herkersdorf, Sören Sonntag, Helmut Reinig
NoC Topology Exploration for Mobile Multimedia Applications
The 16th IEEE International Conference on Electronics, Circuits and Systems
2009

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Christian Köhler, Albrecht Mayer, Andreas Herkersdorf
Chip Hardware-in-the-Loop Simulation (CHILS) Coupling Optimization through new Algorithm Analysis Technique
Proceedings 16th International Conference Mixed Design of Integrated Circuits and Systems
2009

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Zhonglei Wang, Andreas Herkersdorf
Flow Analysis on Intermediate Source Code for WCET Estimation of Compiler-Optimized Programs
The 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)
2009

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Christopher Claus, Robert Huitl, Joachim Rausch, Walter Stechele
Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation
19th International Conference on Field Programmable Logic and Applications (FPL)
2009