User: Guest  Login
Document type:
Konferenzbeitrag 
Author(s):
Zhang, G. L. and Brunner, M. and Li, B. and Sigl, G.and Schlichtmann, U. 
Title:
Timing Resilience for Efficient and Secure Circuits 
Pages contribution:
623-628 
Abstract:
With recent advances in reverse engineering, attackers can reconstruct a netlist to counterfeit chips by opening the die and scanning all layers of authentic chips. This relatively easy counterfeiting is made possible by the use of the standard simple clocking scheme, where all combinational blocks function within one clock period, so that a netlist of combinational logic gates and flip-flops is sufficient to duplicate a design. In this paper, we propose to invalidate the assumption that a netl...    »
 
Dewey Decimal Classification:
620 Ingenieurwissenschaften 
Book / Congress title:
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) 
Congress (additional information):
Beijing, China 
Date of congress:
13.01.-16.01.2020 
Year:
2020 
Quarter:
1. Quartal 
Year / month:
2020-01 
Month:
Jan 
Pages:
623-628 
Reviewed:
ja 
Language:
en