High parallelism and flexibility have turned the Multi-Processors System-on-Chip (MPSoCs) into one of the key enabling technologies for new computational paradigms such as Internet-of-Things (IoT) and Machine Learning. Given the continuous and wide distribution of MPSoC devices together with the MPSoC utilization in critical and sensitive applications, data confidentiality and privacy are of utmost importance. However, with the growing complexity of MPSoCs, the risk of Malware infections and code injection at booting and operation time increases significantly. A persistent threat to MPSoCs security is the configuration of critical MPSoC infrastructures, such as security frameworks (on-chip firewalls and routers). In this work, we propose an infrastructure able to ensure secure booting and dynamic MPSoC operation. To this end, we present two contributions. First, we integrate lightweight security infrastructure based on firewalls and lightweight authenticated encryption. Second, we explore the design space of the security infrastructure and evaluate the impact on the overall performance and cost of the system. In contrast with previous works we explore the fine and coarse grained reconfiguration and show the impact of the location of the security manager in the overall system performance.     «

High parallelism and flexibility have turned the Multi-Processors System-on-Chip (MPSoCs) into one of the key enabling technologies for new computational paradigms such as Internet-of-Things (IoT) and Machine Learning. Given the continuous and wide distribution of MPSoC devices together with the MPSoC utilization in critical and sensitive applications, data confidentiality and privacy are of utmost importance. However, with the growing complexity of MPSoCs, the risk of Malware infections and...     »