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Dokumenttyp:
Patent
Patentanmeldung Nr.:
US 8084759 B2
Erfinder:
KLOSTERMANN ULRICH ; SCHWERIN ULRIKE GRUENING-VON ; KREUPL FRANZ
Patentanmelder:
KLOSTERMANN ULRICH ; SCHWERIN ULRIKE GRUENING-VON ; KREUPL FRANZ
Titel:
Integrated circuit including doped semiconductor line having conductive cladding
Abstract:
An integrated circuit includes an array of memory cells and a doped semiconductor line formed in a semiconductor substrate. The doped semiconductor line is coupled to a row of memory cells. The integrated circuit includes conductive cladding contacting the doped semiconductor line.
Anmeldeland:
US
Veröffentlichungsdatum / Patent:
27.12.2011
Jahr:
2011
Sprache:
en
TUM Einrichtung:
Hybride Elektronische Systeme
Format:
Text
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